< draft-ietf-trill-fine-labeling-01.txt   draft-ietf-trill-fine-labeling-02.txt >
TRILL Working Group Donald Eastlake TRILL Working Group Donald Eastlake
INTERNET-DRAFT Mingui Zhang INTERNET-DRAFT Mingui Zhang
Intended status: Proposed Standard Huawei Intended status: Proposed Standard Huawei
Updates: 6325 Puneet Agarwal Updates: 6325, 6327 Puneet Agarwal
Broadcom Broadcom
Radia Perlman Radia Perlman
Intel Labs Intel Labs
Dinesh Dutt Dinesh Dutt
Expires: December 8, 2012 June 9, 2012 Cumulus Networks
Expires: April 20, 2012 October 21, 2012
TRILL: Fine-Grained Labeling TRILL: Fine-Grained Labeling
<draft-ietf-trill-fine-labeling-01.txt> <draft-ietf-trill-fine-labeling-02.txt>
Abstract Abstract
The IETF has standardized TRILL (TRansparent Interconnection of Lots The IETF has standardized TRILL (TRansparent Interconnection of Lots
of Links), a protocol for least cost transparent frame routing in of Links), a protocol for least cost transparent frame routing in
multi-hop networks with arbitrary topologies and link technologies, multi-hop networks with arbitrary topologies and link technologies,
using link-state routing and encapsulation with a hop count. using link-state routing and encapsulation with a hop count.
The TRILL base protocol standard supports labeling of TRILL data with The TRILL base protocol standard supports labeling of TRILL data with
up to 4K IDs. However, there are applications that require more fine- up to 4K IDs. However, there are applications that require more fine-
grained labeling of data. This document updates RFC 6325 by grained labeling of data. This document updates RFC 6325 and 6327 by
specifying extensions to the TRILL base protocol to accomplish this. specifying extensions to the TRILL base protocol to safely accomplish
this.
Status of This Memo Status of This Memo
This Internet-Draft is submitted to IETF in full conformance with the This Internet-Draft is submitted to IETF in full conformance with the
provisions of BCP 78 and BCP 79. provisions of BCP 78 and BCP 79.
Distribution of this document is unlimited. Comments should be sent Distribution of this document is unlimited. Comments should be sent
to the TRILL working group mailing list. to the TRILL working group mailing list.
Internet-Drafts are working documents of the Internet Engineering Internet-Drafts are working documents of the Internet Engineering
skipping to change at page 2, line 11 skipping to change at page 2, line 11
http://www.ietf.org/1id-abstracts.html. The list of Internet-Draft http://www.ietf.org/1id-abstracts.html. The list of Internet-Draft
Shadow Directories can be accessed at Shadow Directories can be accessed at
http://www.ietf.org/shadow.html. http://www.ietf.org/shadow.html.
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
Table of Contents Table of Contents
1. Introduction............................................3 1. Introduction............................................3
1.1 Terminology............................................3 1.1 Terminology............................................3
1.2 Contributors...........................................4
2. Fine-Grained Labeling...................................4 2. Fine-Grained Labeling...................................5
2.1 Requirements...........................................4 2.1 Goals..................................................5
2.2 Base Protocol TRILL Data Labeling......................5 2.2 Base Protocol TRILL Data Labeling......................6
2.3 Fine-Grained Labeling (FGL)............................5 2.3 Fine-Grained Labeling (FGL)............................7
3. Campus Wide VL versus FGL Semantic Differences..........7 3. Campus Wide VL versus FGL Semantic Differences..........9
4. Interaction with VL TRILL Switches.....................10
4. Coexistence with VL TRILL Switches......................8 5. Fine-Grained Labeling Details..........................12
4.1 VL Specifiable Data Labels.............................8 5.1 Ingress Processing....................................12
5.2 Transit Processing....................................12
5.2.1 Unicast Transit Processing..........................13
5.2.2 Multi-Destination Transit Processing................13
5.3 Egress Processing.....................................13
5.4 Appointed Forwarders and the DRB......................14
5.5 Address Learning......................................14
5.6 ESADI Extensions......................................14
5. Fine-Grained Labeling Details..........................10 6. IS-IS Extensions.......................................16
5.1 Ingress Processing....................................10 7. Comparison to Goals....................................17
5.2 Transit Processing....................................11
5.2.1 Unicast Transit Processing..........................11
5.2.2 Multi-Destination Transit Processing................11
5.3 Egress Processing.....................................12
5.4 Appointed Forwarders and the DRB......................13
5.5 Address Learning......................................13
5.6 ESADI Extensions......................................13
6. IS-IS Extensions.......................................14 8. Allocation Considerations..............................18
7. Comparison to Requirements.............................15 8.1 IEEE Allocation Considerations........................18
8.2 IANA Considerations...................................18
8. Allocation Considerations..............................16 9. Security Considerations................................19
8.1 IEEE Allocation Considerations........................16
8.2 IANA Considerations...................................16
9. Security Considerations................................17 Acknowledgements..........................................19
Acknowledgements..........................................17 Normative References......................................20
Normative References......................................18 Informative References....................................20
Informative References....................................18 Change History............................................21
Change History............................................19
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1. Introduction 1. Introduction
The IETF has standardized the TRILL (TRansparent Interconnection of The IETF has standardized the TRILL (TRansparent Interconnection of
Lots of Links) protocol [RFC6325]. TRILL switches provide a solution Lots of Links) protocol [RFC6325]. TRILL switches provide a solution
for least cost transparent frame routing in multi-hop networks with for least cost transparent routing in multi-hop networks with
arbitrary topologies and link technologies, using [IS-IS] [RFC6165] arbitrary topologies and link technologies, using [IS-IS] [RFC6165]
[RFC6326bis] link-state routing and encapsulation with a hop count. [RFC6326bis] link-state routing and encapsulation with a hop count.
They address the problems outlined in [RFC5556]. TRILL switches are They address the problems outlined in [RFC5556]. TRILL switches are
sometimes called RBridges (Routing Bridges). sometimes called RBridges (Routing Bridges).
The TRILL base protocol standard supports labeling of TRILL data with The TRILL base protocol standard supports labeling of TRILL data with
up to 4K IDs. However, there are applications that require more fine- up to 4K IDs. However, there are applications that require more fine-
grained labeling of data for configurable isolation based on grained labeling of data for configurable isolation based on
different service instances, tenants, or the like. This document different tenants, service instances, or the like. This document
updates [RFC6325] by specifying extensions to the TRILL base protocol updates [RFC6325] and [RFC6327] by specifying extensions to the TRILL
to accomplish this. base protocol to safely accomplish this.
Familiarity with [RFC6325] and [RFC6326bis] is assumed in this Familiarity with [RFC6325] and [RFC6326bis] is assumed in this
document. document.
1.1 Terminology 1.1 Terminology
The terminology and acronyms of [RFC6325] are used in this document The terminology and acronyms of [RFC6325] are used in this document
with the additions listed below. with the additions listed below.
DEI - Drop Eligibility Indicator [802.1Q] DEI - Drop Eligibility Indicator [802.1Q]
skipping to change at page 4, line 7 skipping to change at page 4, line 7
VL RBridge - A TRILL switch that supports VL but does not support VL RBridge - A TRILL switch that supports VL but does not support
FGL FGL
The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT",
"SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this
document are to be interpreted as described in [RFC2119]. document are to be interpreted as described in [RFC2119].
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1.2 Contributors
Thanks for the contributions of the following:
Tissa Senevirathne
INTERNET-DRAFT TRILL: Fine-Grained Labeling
2. Fine-Grained Labeling 2. Fine-Grained Labeling
The essence of Fine-Grained Labeling (FGL) is that (a) when TRILL The essence of Fine-Grained Labeling (FGL) is that (a) when TRILL
Data frames are ingressed or created they may incorporate a label Data frames are ingressed or created they may incorporate a label
from a set of significantly more than 4K labels, (b) TRILL switch from a set consisting of significantly more than 4K labels, (b) TRILL
ports can be labeled with a set of such labels, and (c) an FGL TRILL switch (RBridge) ports can be labeled with a set of such labels, and
Data frame cannot be egressed through a TRILL switch port unless its (c) an FGL TRILL Data frame cannot be egressed through an RBridge
fine-grained label (FGL) matches one of the labels of the port. port unless its fine-grained label (FGL) matches one of the labels of
the port.
Section 2.1 lists FGL requirements. Section 2.2 briefly outlines the Section 2.1 lists FGL goals. Section 2.2 briefly outlines the more
more coarse TRILL base protocol standard [RFC6325] data labeling. And coarse TRILL base protocol standard [RFC6325] data labeling. And
Section 2.3 outlines a method of FGL of TRILL Data frames. Section 2.3 outlines a method of FGL of TRILL Data frames.
2.1 Requirements 2.1 Goals
There are several requirements that should be met by FGL in TRILL. There are several goals that should be met by FGL in TRILL. They are
They are briefly described in the list below in approximate order by briefly described in the list below in approximate order by priority
priority with the most important first. with the most important first.
1. Fine-Grained 1. Fine-Grained
Some networks have a large number of entities that need Some networks have a large number of entities that need
configurable isolation, whether those entities are independent configurable isolation, whether those entities are independent
customers, applications, or branches of a single endeavor or some customers, applications, or branches of a single endeavor or some
combination of these or other entities. The labeling supported by combination of these or other entities. The labeling supported by
[RFC6325] provides for only ( 2**12 - 2 ) valid identifiers or [RFC6325] provides for only ( 2**12 - 2 ) valid identifiers or
labels. A substantially larger number is required. labels. A substantially larger number is required.
2. Silicon Considerations 2. Silicon Considerations
Fine-grained labeling (FGL) should, to the extent practical, use Fine-grained labeling (FGL) should, to the extent practical, use
existing features, processing, and fields that are already existing features, processing, and fields that are already
supported in at least some TRILL fast path silicon supported in at least some fast path silicon implementations that
implementations. currently support the TRILL base protocol.
3. Base RBridge Compatibility 3. Base RBridge Compatibility
To support some incremental conversion scenarios, it is desirable To support some incremental conversion scenarios, it is desirable
that not all RBridges in a campus using FGL be required to be FGL that not all RBridges in a campus using FGL be required to be FGL
aware. That is, it is desirable that RBridges not implementing the aware. That is, it is desirable that RBridges not implementing the
FGL feature and performing at least the transit forwarding FGL feature and performing at least the transit forwarding
function can usefully process TRILL Data frames that incorporate function can usefully process TRILL Data frames that incorporate
FGL. FGL.
INTERNET-DRAFT TRILL: Fine-Grained Labeling
4. Alternate Priority 4. Alternate Priority
It would be desirable for an ingress TRILL Switch to be able to It would be desirable for an ingress TRILL Switch to be able to
assign a different priority to an FGL TRILL Data frame for its assign a different priority to an FGL TRILL Data frame for its
INTERNET-DRAFT TRILL: Fine-Grained Labeling
ingress-to-egress propagation from the priority of the original ingress-to-egress propagation from the priority of the original
native frame. The original priority should be restored on egress. native frame. The original priority should be restored on egress.
2.2 Base Protocol TRILL Data Labeling 2.2 Base Protocol TRILL Data Labeling
This section provides a brief review of the [RFC6325] TRILL Data This section provides a brief review of the [RFC6325] TRILL Data
frame internal VL Labeling and changes the description of the TRILL frame internal VL Labeling and changes the description of the TRILL
Header by moving its end point. This description change does not Header by moving its end point. This description change does not
involve any change in the bits on the wire or in the behavior of involve any change in the bits on the wire or in the behavior of
existing [RFC6325] RBridges. existing [RFC6325] RBridges.
Currently TRILL Data frames have the VL structure shown below: Currently TRILL Data frames have the VL structure shown below:
+-------------------------------------------+ +-------------------------------------------+
| Link Header (depends on link technology) | | Link Header (depends on link technology) |
| (may include VLAN tag if an Ethernet link)| | (if link is an Ethernet link the link |
| header may include an Outer.VLAN tag) |
+-------------------------------------------+ +-------------------------------------------+
| TRILL Header | | TRILL Header |
| +---------------------------------------+ | | +---------------------------------------+ |
| | Initial Fields and Options | | | | Initial Fields and Options | |
| +---------------------------------------+ | | +---------------------------------------+ |
| | Inner.MacDA | (6 bytes) | | | Inner.MacDA | (6 bytes) |
| +-----------------------------+ | | +-----------------------------+ |
| | Inner.MacSA | (6 bytes) | | | Inner.MacSA | (6 bytes) |
| +-----------------------------+ | | +-----------------------+-----+ |
| | EtherType 0x8100 | (2 bytes) | | | Ethertype 0x8100 | (2 bytes) |
| +-------------------------+ | | +-----------------------+ |
| | Inner.VLAN Label | (2 bytes) | | | Inner.VLAN Label | (2 bytes) |
| +-------------------------+ | | +-----------------------+ |
+-------------------------------------------+ +-------------------------------------------+
| Native Payload | | Native Payload |
+-------------------------------------------+ +-------------------------------------------+
| Link Trailer (depends on link technology) | | Link Trailer (depends on link technology) |
+-------------------------------------------+ +-------------------------------------------+
As specified in [RFC6325] the 0x8100 value is always present and is Figure 1. TRILL Data with VL
followed by the Inner.VLAN field which includes the 12-bit VLAN
label.
2.3 Fine-Grained Labeling (FGL)
FGL expands the data label available under the TRILL base protocol In the base protocol as specified in [RFC6325] the 0x8100 value is
standard to a fine-grained label with a 12-bit high order part and a always present and is followed by the Inner.VLAN field which includes
12-bit low order part. In this document, FGLs are usually denoted as the 12-bit VL.
"(X.Y)" where X is the high order part and Y is the low order part of
the FGL. The FGL information appears in the TRILL Header as shown
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below. 2.3 Fine-Grained Labeling (FGL)
FGL expands the data label available under the TRILL base protocol
standard to a fine-grained label (FGL) with a 12-bit high order part
and a 12-bit low order part. In this document, FGLs are usually
denoted as "(X.Y)" where X is the high order part and Y is the low
order part of the FGL. The FGL information appears in the TRILL
Header as shown below.
+-------------------------------------------+ +-------------------------------------------+
| Link Header (depends on link technology) | | Link Header (depends on link technology) |
| (may include VLAN tag if an Ethernet link)| | (if link is an Ethernet link the link |
| header may include an Outer.VLAN tag) |
+-------------------------------------------+ +-------------------------------------------+
| TRILL Header | | TRILL Header |
| +---------------------------------------+ | | +---------------------------------------+ |
| | Initial Fields and Options | | | | Initial Fields and Options | |
| +---------------------------------------+ | | +---------------------------------------+ |
| | Inner.MacDA | (6 bytes) | | | Inner.MacDA | (6 bytes) |
| +-----------------------------+ | | +-----------------------------+ |
| | Inner.MacSA | (6 bytes) | | | Inner.MacSA | (6 bytes) |
| +-----------------------------+ | | +-----------------------+-----+ |
| | EtherType 0x8100 | (2 bytes) | | | Ethertype 0x893B | (2 bytes) |
| +-------------------------+ | | +-----------------------+ |
| | Inner.Label High Part | (2 bytes) | | | Inner.Label High Part | (2 bytes) |
| +-------------------------+ | | +-----------------------+ |
| | EtherType 0x893B | (2 bytes) | | | Ethertype 0x893B | (2 bytes) |
| +-------------------------+ | | +-----------------------+ |
| | Inner.Label Low Part | (2 bytes) | | | Inner.Label Low Part | (2 bytes) |
| +-------------------------+ | | +-----------------------+ |
+-------------------------------------------+ +-------------------------------------------+
| Native Payload | | Native Payload |
+-------------------------------------------+ +-------------------------------------------+
| Link Trailer (depends on link technology) | | Link Trailer (depends on link technology) |
+-------------------------------------------+ +-------------------------------------------+
The fixed format area of the TRILL Header with the Inner.Label parts Figure 2. TRILL Data with FGL
and EtherType fields 0x8100 and 0x893B is mandatory for FGL frames.
It is designed for backward compatibility with [RFC6325] conformant
RBridges although such RBridges will only be aware of the high order
12-bits of the FGL.
The two bytes following the EX-TAG EtherType 0x893B have, in their For FGL frames, the inner MAC address fields are followed by the FGL
low order 12 bits, the low order part of the fine-grained label. The information using 0x893B.
upper 4 bits of those two bytes are used for a 3-bit priority field
and one drop eligibility indicator (DEI) bit. The two bytes following each 0x893B have, in their low order 12 bits,
fine-grained label information. The upper 4 bits of those two bytes
are used for a 3-bit priority field and one drop eligibility
indicator (DEI) bit.
The priority field of the Inner.Label High Part is the priority used The priority field of the Inner.Label High Part is the priority used
for frame transport from ingress to egress. for frame transport across the TRILL campus from ingress to egress.
The label bits in the Inner.Label High Part are the high order part
of the FGL and those bits in the Inner.Label Low Part are the low
INTERNET-DRAFT TRILL: Fine-Grained Labeling
order part of the FGL.
The appropriate FGL value for an ingressed native frame is determined The appropriate FGL value for an ingressed native frame is determined
by the ingress RBridge port as specified in Section 5.1. Ports of by the ingress RBridge port as specified in Section 5.1. Ports of
TRILL switches supporting FGL also have capabilities to transmit TRILL switches supporting FGL also have capabilities to transmit
frames being forwarded or egressed as untagged or VLAN tagged as frames being forwarded or egressed as untagged or VL as specified in
specified in Section 5.3. Section 5.3.
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3. Campus Wide VL versus FGL Semantic Differences 3. Campus Wide VL versus FGL Semantic Differences
There are significant differences between the semantics across a There are differences between the semantics across a TRILL campus for
campus for VLs and FGLs of TRILL Data frames. VL and FGL labeled TRILL Data frames.
With VL, data label IDs have the same meaning throughout the campus With VL, data label IDs have the same meaning throughout the campus
and are from the same label space as the VLAN IDs used on Ethernet and are from the same label space as the VLAN IDs used on Ethernet
links to end stations. links to end stations.
With TRILL FGL, many things remain the same. Ports of FGL TRILL With TRILL FGL, many things remain the same. Ports of FGL TRILL
switches, at and below the EISS (Extended Internal Sublayer Service) switches, up through the usual VLAN and priority processing, act as
interface, act as they do for VL RBridges: Ethernet links between FGL they do for VL TRILL switches: Ethernet links between FGL TRILL
TRILL switches still have only C-VLAN tagging on them and the EISS of switches still have only C-VLAN tagging on them and TRILL switch
TRILL switch ports provide a VLAN ID for an incoming frame and ports provide a VLAN ID for an incoming frame and accepts a VLAN ID
accepts a VLAN ID for a frame being queued for output. Appointed for a frame being queued for output. Appointed Forwarders [RFC6439]
Forwarders [RFC6439] on a link are still appointed for a C-VLAN. The on a link are still appointed for a C-VLAN. The Designated VLAN for
Designated VLAN for an Ethernet link is still a C-VLAN. an Ethernet link is still a C-VLAN.
The larger FGL space is a different space from the VL data label The larger FGL space is a different space from the VL data label
space. For ports configured for FGL, the C-VLAN on an ingressed space. For ports configured for FGL, the C-VLAN on an ingressed
native frame is mapped to the FGL data label space with a potentially native frame is mapped to the FGL data label space with a potentially
different mapping for each port. A similar FGL to C-VLAN mapping different mapping for each port. A similar FGL to C-VLAN mapping
occurs per port on egress. Thus, for ports configured for FGL, the occurs per port on egress. Thus, for ports configured for FGL, the
native frame C-VLAN on one link corresponding to an FGL can be native frame C-VLAN on one link corresponding to an FGL can be
different from the native frame C-VLAN corresponding to that same FGL different from the native frame C-VLAN corresponding to that same FGL
on a different link elsewhere in the campus or even a different link on a different link elsewhere in the campus or even a different link
attached to the same RBridge. The FGL label space is flat and does attached to the same RBridge. The FGL label space is flat and does
not hierarchically encode any particular number of native frame C- not hierarchically encode any particular number of native frame C-
VLAN bits or the like. FGLs in TRILL Data frames appear only inside VLAN bits or the like. FGLs in TRILL Data frames appear only inside
the payload after the TRILL Header. As a result, they are only seen the TRILL Header after the inner MAC addresses. They are only seen by
by TRILL aware devices. TRILL aware devices.
FGL RBridge ports can be configured for FGL or VL with VL being the FGL RBridge ports can be configured for FGL or VL with VL being the
default. As with a base protocol [RFC6325] RBridge, an unconfigured default. As with a base protocol [RFC6325] RBridge, an unconfigured
FGL TRILL switch port reports an untagged frame it receives as being FGL TRILL switch port reports an untagged frame it receives as being
in VLAN 1. in VLAN 1.
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
4. Coexistence with VL TRILL Switches 4. Interaction with VL TRILL Switches
Unmodified VL RBridges will operate properly as transit TRILL
switches. Transit TRILL switches look at the VL or FGL data labeling
only for pruning the distribution of multi-destination frames. If an
RBridge does not perform pruning, or prunes on only part of the
fields in the packet, the only consequence is that multi-destination
frames will use more bandwidth than necessary. VL RBridges would only
look at the high order X of the (X.Y) FGL, which are in the position
where a VL RBridge would expect to find a VL data label. Thus they
will not be able to prune as effectively as transit FGL TRILL
switches could because they will ignore the lower order half of the
FGL. (Transit RBridge that fully support FGL can, of course, prune on
the full FGL.)
To avoid potential problems with VL RBridges, the high order X of an
(X.Y) FGL MUST NOT be zero or 0xFFF.
It would be more serious if a VL edge RBridge, RB1, unaware of FGL,
forwarded an FGL frame with FGL (X.Y) onto a link through an RB1 port
configured as VL VLAN-X. VL RB1 would strip the TRILL Header only
through the Inner.Label First Part and forward the packet with the
Inner.Label Second Part and preceding 0x893B field still present.
This might cause other problems on the link. It would also be
problematic if a malicious end station could forge an apparent FGL
(X.Y) frame by including extra fields in native frames ingressed by a
VL edge RBridge. Therefore, it is highly desirable for all the edge
RBridges to be FGL TRILL switches.
FGL RBridge will report the FGL capability in LSPs, so FGL RBridges It is not possible for VL TRILL switches to handle FGL frames even if
(and any management system with access to the link state database) the VL TRILL switch is only acting in the transit capacity. This is
will be able to detect the existence of VL edge RBridges. because VL frames are required to have 0x8100 at the beginning of the
data label where FGL TRILL switches have 0x893B. VL-only TRILL
switches conformant to [RFC6325] should discard frames with this new
value after the inner MAC addresses and, if they do not discard such
frames, they will be confused (see Section 9 below).
4.1 VL Specifiable Data Labels If there are FGL TRILL switches in a campus, it is assumed that the
intent is for all TRILL switches in that campus to support FGL. Any
VL TRILL switches present are isolated by FGL TRILL switches as
follows: FGL RBridges will report their FGL capability in LSPs. Thus
FGL TRILL switches (and any management system with access to the link
state database) will be able to detect the existence of TRILL
switches in the campus that do not support FGL. If any such VL TRILL
switches are present on a link then, although all other aspects of
the adjacency machinery work as normal [RFC6327], any FGL TRILL
switches on the link will not create a pseudo node for the link if
they are DRB and do not announce any adjacencies they have on the
link. As a result, although adjacencies between two or more VL
RBridge ports on the link could become part of the campus topology
and pass TRILL Data frames, no adjacency from an FGL RBridge port to
a VL RBridge port or to a pseudonode will be reported for such a
mixed FGL/VL link. Since an adjacency must be reported up by both
ends before it becomes part of the campus topology, even though
adjacencies to an FGL RBridge might be reported by a VL RBridge, no
TRILL Data can flow between an FGL RBridge port and a VL RBridge
port.
It might be useful, in a particular campus with mixed VL and FGL The usual DRB election operates on a link with mixed FLG and VL
TRILL switches, to have some end station VLANs accessible via VL edge ports. If an FGL RBridge port is DRB, it MUST handle all native
RBridges. This is supported by reserving some number of VLANs (say traffic or appoint only other FGL ports as forwarder for one or more
the first k), to be VL-addressable. These VLANs will be specified VLANs, so that all end stations will get service to the FGL campus.
with a VL data label, whether or not any of the edge TRILL switches If a VL RBridge port is DRB, it will not understand that FGL RBridge
attached to these end station VLANs are FGL-capable. When VL- ports are different. To the extent that a VL DRB handles native
specifiable VLANs are used in a FGL campus the upper part of an FGL frames or appoints other VL ports on a link to handle native frames
MUST NOT be equal to the value of any VL-specifiable data label. for one or more VLANs, the end stations sending and receiving those
native frames will be isolated from the FGL campus. To the extent
that a VL DRB happens to appoint an FGL port as Appointed Forwarder
for one or more VLANs, the end stations sending and receiving native
frames in those VLANs will get service to the FGL campus. This
somewhat odd corner case behavior is considered acceptable because it
is assumed that VL TRILL switches in an FGL campus are infrequent
misconfigurations.
If this rule is violated, the network misconfiguration is detected by For links configured as point-to-point, if the TRILL switches at each
the FGL TRILL switches that will then refuse in ingress to or egress end are both VL or both FGL, a bi-directional adjacency can be formed
from label (X.Y) while end station VLAN X connectivity is VL- by the usual mechanisms. If one is VL and one is FGL but the point-
specifiable as described below.
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
To avoid FGL frames getting pruned by VL RBridges, an FGL RBridge to-point link is otherwise correctly configured, the VL TRILL switch
that ingresses to or egresses from (X.Y) MUST advertise in its LSP will report an adjacency but the LFG one will not. As a result, the
that it is connected to VLAN X. To avoid confusion, it is necessary link will not become part of the topology and TRILL Data cannot flow
to distinguish whether a TRILL switch is advertising VL-specifiable over the link, isolating the VL TRILL switch.
connectivity to VLAN X or just advertising such connectivity to avoid
incorrect VL RBridge pruning. This is determined by whether or not
the FLG RBridge advertising connectivity to VLAN X is also
advertising connectivity to (X.Y) for some Y.
A VL data label X is VL-specifiable in a campus if either of the
following two conditions apply:
1. A VL RBridge advertises connectivity to VLAN-X.
2. An FGL RBridge advertises connectivity to VLAN-X but does not
advertise connectivity to FGL (X.Y) for any Y.
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
5. Fine-Grained Labeling Details 5. Fine-Grained Labeling Details
This section specifies ingress, transit, egress, and other processing This section specifies ingress, transit, egress, and other processing
of TRILL Data frames with regard to Fine-Grained Labels (FGLs). A of TRILL Data frames with regard to FGLs. A transit or egress FGL
transit or egress FGL TRILL switch detects FGL TRILL Data frames by TRILL switch determines that a TRILL Data frame is FGL by detecting
noticing that the Inner.Label High Part is not a VL-specifiable data that the inner MAC address fields are followed by 0x893B.
label (see Section 4.1).
5.1 Ingress Processing 5.1 Ingress Processing
An FGL RBridge may be configured, on one or more ports, to FGL An FGL RBridge MAY be configured, on one or more ports, to ingress
ingress native frames. There is no change in VL ingress processing, native frames as FGL. Any ports not so configured that accepts a
which is the default unless a port has been configured for FGL, and native frame perform the previously specified VL ingress processing
no change in Appointed Forwarder logic (see Section 5.4). on native frames [RFC6325]. There is no change in Appointed
Forwarder logic (see Section 5.4).
FGL TRILL switches MUST support configurable per port mapping from FGL TRILL switches MUST support configurable per port mapping from
the C-VLAN ID of a native frame, as reported by the ingress port, to the VL of a native frame, as reported by the ingress port, to an FGL.
an FGL. FGL TRILL switches MAY support other methods to determine the FGL TRILL switches MAY support other methods to determine the FGL of
FGL of an incoming native frame, such as based on the protocol of the an incoming native frame, such as based on the protocol of the native
native frame. If the resulting label (X.Y) is such that X is a VL- frame or local knowledge.
specifiable data label, the ingressed frame MUST be dropped.
The FGL ingress process MUST place the priority and DEI associated The FGL ingress process MUST place the priority and DEI associated
with an ingressed native frame in upper 4 bits of the Low Order with an ingressed native frame in upper 4 bits of the Inner.Label Low
Inner.Label part. It SHOULD also associate a possibly different Order part. It SHOULD also associate a possibly different mapped
mapped priority and DEI with an ingressed frame. The mapped priority priority and DEI with an ingressed frame. The mapped priority is
is placed in the Inner.Label High Part. If such mapping is not placed in the Inner.Label High Part. If such mapping is not supported
supported then the original priority and DEI MUST be placed in the then the original priority and DEI MUST be placed in the Inner.Label
Inner.Label High Part. High Part.
An FGL ingress RBridge MAY serially TRILL unicast a multi-destination An FGL ingress RBridge MAY serially TRILL unicast a multi-destination
TRILL Data frame to the relevant egress TRILL switches, if those TRILL Data frame to the relevant egress TRILL switches after
egress RBridges are all FGL, after encapsulating it as a TRILL known encapsulating it as a TRILL known unicast data frame (M=0) and SHOULD
unicast data frame (M=0) and SHOULD so unicast such a multi- unicast such a multi-destination TRILL Data frame if there is only
destination TRILL Data frame if there is only one relevant egress FGL one relevant egress FGL RBridge. For FGL RBridges, this permits
RBridge. For FGL RBridges, this permits serial unicast of multi- serial unicast of multi-destination frames by the ingress as an
destination frames by the ingress as an alternative to the use of a alternative to the use of a distribution tree. The relevant egress
distribution tree. The relevant egress TRILL switches are determined TRILL switches are determined by starting with those announcing
by starting with those announcing connectivity to the frame's (X.Y) connectivity to the frame's (X.Y) label. That set SHOULD be further
label. That set SHOULD be further filtered based on multicast filtered based on multicast listener and multicast router
listener and router connectivity if the native frame was a multicast connectivity if the native frame was a multicast frame.
frame.
Use of S-tags is beyond the scope of this document but is an obvious
extension.
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5.2 Transit Processing 5.2 Transit Processing
TRILL Data frame transit processing is fairly straightforward as TRILL Data frame transit processing is fairly straightforward as
described in Section 5.2.1 for known unicast TRILL Data frames and in described in Section 5.2.1 for known unicast TRILL Data frames and in
Section 5.2.2 for multi-destination TRILL Data frames. Section 5.2.2 for multi-destination TRILL Data frames.
INTERNET-DRAFT TRILL: Fine-Grained Labeling
5.2.1 Unicast Transit Processing 5.2.1 Unicast Transit Processing
There is almost no change in TRILL Data frame unicast transit There is very little change in TRILL Data frame unicast transit
processing. A transit TRILL switch forwards any unicast TRILL Data processing. A transit TRILL switch forwards any unicast TRILL Data
frame to the next hop towards the egress RBridge as specified in the frame to the next hop towards the egress RBridge as specified in the
TRILL Header. Just as transit RBridges conformant to the TRILL base TRILL Header. All transit TRILL switches, whether VL or FGL, MUST
protocol standard [RFC6325] do not examine the VL of unicast TRILL take the priority and DEI used to forward a frame from the Inner.VLAN
Data frames, transit FGL RBridges do not examine the FGL of unicast label or the FGL Inner.Label High Part. These bits are in the same
TRILL Data frames. place in the frame.
All transit TRILL switches, whether VL or FGL, MUST take the priority
and DEI used to forward a frame from the Inner.VLAN label or the FGL
Inner.Label High Part. These bits are in the same relative position
for VL and FGL frames so VL RBridges will do this automatically even
though they do not fully understand FGL frames.
5.2.2 Multi-Destination Transit Processing 5.2.2 Multi-Destination Transit Processing
Multi-destination TRILL Data frames are forwarded on a distribution Multi-destination TRILL Data frames are forwarded on a distribution
tree selected by the ingress TRILL switch except that an FGL ingress tree selected by the ingress TRILL switch except that an FGL ingress
RBridge MAY choose to TRILL unicast such a frame to all relevant RBridge MAY choose to TRILL unicast such a frame to all relevant
egress TRILL switches if they are all support FGL. The distribution egress TRILL switches. The distribution trees do not distinguish
trees for FGL and VL multi-destination frames are the same and are between FGL and VL multi-destination frames except, possibly, in
calculated as provided for in the TRILL base protocol standard pruning behavior. All distribution trees are calculated as provided
[RFC6325]. There is no change in the Reverse Path Forwarding Check. for in the TRILL base protocol standard [RFC6325]. There is no change
in the Reverse Path Forwarding Check.
An FGL RBridge, say RB1, having an FGL multi-destination frame for An FGL RBridge, say RB1, having an FGL multi-destination frame for
label (X.Y) to forward on a distribution tree, SHOULD prune that tree label (X.Y) to forward on a distribution tree, SHOULD prune that tree
based on whether there are any edge TRILL switches on a tree branch based on whether there are any edge TRILL switches on a tree branch
that are advertising connectivity to label (X.Y). In addition, RB1 that are advertising connectivity to label (X.Y). In addition, RB1
SHOULD prune multicast frames based on reported multicast listener SHOULD prune multicast frames based on reported multicast listener
and multicast router attachment in (X.Y). Finally, a transit FGL and multicast router attachment in (X.Y).
RBridge MAY drop any multi-destination frame for label (X.Y) if X is
VL-specifiable (see Section 4.1). "MAY" is chosen in this case to
minimize the checking burden on transit TRILL switches.
To ensure that a transit VL RBridge does not falsely filter traffic
for FGL (X.Y), an FGL edge RBridge reporting connectivity to FGL
(X.Y) MUST report connection to VLAN X as well. Because of this, VL
transit RBridges can safely apply pruning to all TRILL Data frames,
INTERNET-DRAFT TRILL: Fine-Grained Labeling
both VL and FGL, based on the reported VLAN-X connectivity of all
downstream TRILL switches.
To ensure that a transit VL RBridge does not falsely prune traffic Pruning is an optimization. If a transit TRILL switch does less
for FGL (X.Y) base on multicast filtering, an FGL edge RBridge pruning than it could, there may be greater link utilization than
attached to label (X.Y) MUST also report for VLAN-X either (1) that strictly necessary but the campus will still operate correctly. For
it is attached to both IPv4 and IPv6 multicast routers or (2) its example, a transit TRILL switch could prune based on only part of the
merged FGL (X.Y) multicast listener and router connectivity for all FGL such as only the High Part or only the Low Part.
Y.
5.3 Egress Processing 5.3 Egress Processing
Egress processing is generally the reverse of ingress progressing Egress processing is generally the reverse of ingress progressing
described in Section 5.1. described in Section 5.1.
If X is VL-specifiable (see Section 4.1), an FGL RBridge MUST NOT
egress a frame with FGL (X.Y) but MUST drop such a frame.
An FGL RBridge MUST be able to configurably convert the FGL in an FGL An FGL RBridge MUST be able to configurably convert the FGL in an FGL
TRILL Data frame it is egressing to a C-VLAN ID for the resulting TRILL Data frame it is egressing to a VLAN ID for the resulting
native frame on a per port basis. A port MAY be configured to strip native frame on a per port basis. A port MAY be configured to strip
output VLAN tagging. It is the responsibility of the network manager output VLAN tagging. It is the responsibility of the network manager
to properly configure the TRILL switches and ports in the campus to to properly configure the TRILL switches in the campus to obtain the
obtain the desired mappings. desired mappings.
INTERNET-DRAFT TRILL: Fine-Grained Labeling
The priority and DEI of the egressed native frame are taken from the The priority and DEI of the egressed native frame are taken from the
Inner.Label Low Order Part. Inner.Label Low Order Part.
An FGL RBridge egresses FGL frames similarly to the egressing of VL An FGL RBridge egresses FGL frames similarly to the egressing of VL
frames, as follows: frames, as follows:
1. A known unicast FGL frame is egressed to the FGL port matching its 1. A known unicast FGL frame is egressed to the FGL port matching its
fine-grained label and Inner.MacDA. If there is no such port, it fine-grained label and Inner.MacDA. If there is no such port, it
is flooded out all FGL ports that have its FGL unless the TRILL is flooded out all FGL ports that have its FGL unless the TRILL
switch has knowledge that the frames Inner.MacDA cannot be out switch has knowledge that the frame's Inner.MacDA cannot be out
that port. that port.
2. A multi-destination FGL frame is decapsulated and flooded out all 2. A multi-destination FGL frame is decapsulated and flooded out all
ports with its FGL, subject to multicast pruning. ports with its FGL, subject to multicast pruning.
FGL RBridges MUST accept multi-destination encapsulated frames that FGL RBridges MUST accept multi-destination encapsulated frames that
are sent to them as TRILL unicast frames, that is, frames with a are sent to them as TRILL unicast frames, that is, frames that may
multicast or broadcast Inner.MacDA and the TRILL Header M bit = 0. have a multicast or broadcast Inner.MacDA (or are being sent to an
They locally egress such frames, if appropriate, but MUST NOT forward unknown unicast Inner.MacDA) and the TRILL Header M bit = 0. They
them (other than egressing them as native frames on their local locally egress such frames, if appropriate, but MUST NOT forward them
links). (other than egressing them as native frames on their local links).
Use of S-tags is beyond the scope of this document but is an obvious
INTERNET-DRAFT TRILL: Fine-Grained Labeling
extension.
5.4 Appointed Forwarders and the DRB 5.4 Appointed Forwarders and the DRB
There is no change in Adjacency [RFC6327] or Appointed Forwarder There is no change in Adjacency [RFC6327] or Appointed Forwarder
logic [RFC6439] on a link regardless of whether some or all the ports logic [RFC6439] on a link regardless of whether some or all the ports
on the link are for FGL RBridges. However, if it is intended for on the link are for FGL RBridges except as described in Section 4
native frames on a link in some VLAN-X to be ingressed and egressed above.
with FGL, the Appointed Forwarder for VLAN-X for that link obviously
MUST be an FGL RBridge.
If there are FGL and VL TRILL switches connected to a link, it may be
best if the priorities are configured so that the DRB is an FGL
RBridge. However, there is no inherent difficulty in a VL DRB RBridge
appointing an FGL TRILL switch connected to the link as Appointed
Forwarder for whatever VLANs are appropriate.
5.5 Address Learning 5.5 Address Learning
An FGL RBridge learns addresses on FGL ports based on the fine- An FGL TRILL switch learns addresses on FGL ports based on the fine-
grained label rather than the native frame's VLAN. Addresses learned grained label rather than the native frame's VLAN. Addresses learned
from ingressed native frames on FGL ports are logically represented from ingressed native frames on FGL ports are logically represented
by { MAC address, fine-grained label, port, confidence, timer } while by { MAC address, fine-grained label, port, confidence, timer } while
remote addresses learned from egressing FGL frames are logically remote addresses learned from egressing FGL frames are logically
represented by { MAC address, fine-grained label, remote TRILL switch represented by { MAC address, fine-grained label, remote TRILL switch
nickname, confidence, timer }. nickname, confidence, timer }.
5.6 ESADI Extensions 5.6 ESADI Extensions
The TRILL ESADI (End Station Address Distribution Information) The TRILL ESADI (End Station Address Distribution Information)
protocol is specified in [RFC6325] as optionally transmitting MAC protocol is specified in [RFC6325] as optionally transmitting MAC
address connection information through TRILL Data frames between address connection information through TRILL Data frames between
INTERNET-DRAFT TRILL: Fine-Grained Labeling
participating TRILL switches over the virtual link provided by the participating TRILL switches over the virtual link provided by the
TRILL multicast frame distribution mechanism. In [RFC6325], the VLAN TRILL multicast frame distribution mechanism. In [RFC6325], the VLAN
to which an ESADI frame applies is indicated only by the Inner.VLAN to which an ESADI frame applies is indicated only by the Inner.VLAN
label and no indication of that VLAN is allowed within the ESADI label and no indication of that VLAN is allowed within the ESADI
payload. payload.
ESADI is extended to support FGL by providing for the indication of ESADI is extended to support FGL by providing for the indication of
the FGL to which an ESADI frame applies only in the Inner.Label of the FGL to which an ESADI frame applies only in the Inner.Label of
that frame and no indication of that FGL is allowed within the ESADI that frame and no indication of that FGL is allowed within the ESADI
payload. payload.
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6. IS-IS Extensions 6. IS-IS Extensions
Extensions to the TRILL use of IS-IS are required to support the Extensions to the TRILL use of IS-IS are required to support FGL
following: include the following:
1. An method for a TRILL switch to announce itself in its LSP as 1. An method for a TRILL switch to announce itself in its LSP as
supporting FGL. supporting FGL.
2. A sub-TLV analogous to Interested VLANs and Spanning Tree Roots 2. A sub-TLV analogous to Interested VLANs and Spanning Tree Roots
sub-TLV of the Router Capabilities TLV but indicating FGLs rather sub-TLV of the Router Capabilities TLV but indicating FGLs rather
than VLANs. than VLs (see Section 8.2). This is called the Interested Labels
and Spanning Tree Roots sub-TLV in [rfc6326bis].
3. A sub-TLV analogous to the GMAC-ADDR sub-TLV of the Group Address
TLV that specifies a FGL rather than a VLAN.
See [RFC6326bis] and Section 8.2. 3. Sub-TLVs analogous to the GMAC-ADDR sub-TLV of the Group Address
TLV that specifies an FGL rather than a VL (see Section 8.2.).
This are called the GLMAC-ADDR, GLIP-ADDR, and GLIP6 ADDR sub-TLVs
in [rfc6326bis].
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
7. Comparison to Requirements 7. Comparison to Goals
Comparing TRILL fine-grained labeling (FGL), as specified in this Comparing TRILL FGL, as specified in this document, with the goals
document, with the requirements given in Section 2.1, we find they given in Section 2.1, we find as follows:
are met as follows:
1. Fine-Grained: FGL provides approaching 2**24 labels, vastly more 1. Fine-Grained: FGL provides 2**24 labels, vastly more labels than
labels than the 4K inner TRILL data labels provided in [RFC6325]. the 4K VL labels provided in [RFC6325].
2. Silicon Considerations: Existing TRILL fast path silicon chips 2. Silicon Considerations: Existing TRILL fast path silicon chips can
can, almost by definition, perform base TRILL Header insertion and perform base TRILL Header insertion and removal to support ingress
removal to support ingress and egress. In addition, it is believed and egress. In addition, it is believed that most such silicon
that most such silicon chips can also perform the native frame C- chips can also perform the native frame to FGL mapping and the
VLAN and port to fine-grained label mapping and the encoding of encoding of the FGL as specified herein, as well as the inverse
the fine-grained label as specified herein, as well as the inverse
decoding and mapping. Some existing silicon can perform only one decoding and mapping. Some existing silicon can perform only one
of these operations on a frame in the fast path and is thus not of these operations on a frame in the fast path and is thus not
suitable to implement fast path TRILL FGL processing; however, suitable to implement fast path TRILL FGL processing; however,
other existing chips are believed to be able to perform both other existing chips are believed to be able to perform both
operations on the same frame in the fast path and are suitable for operations on the same frame in the fast path and are suitable for
FGL implementation. FGL implementation.
3. Base RBridge Compatibility: As described in Section 3, FGL is 3. Base RBridge Compatibility: As described in Section 3, FGL is not
compatible with base specification (VL) RBridges [RFC6325] acting compatible with TRILL switches conformant to the base
as transit TRILL switches and, as described in Section 5.4, there specification RBridges [RFC6325].
is no particular problem in mixing VL and FGL TRILL switches on
the same link.
4. Alternate Priority: The encoding specified in Section 2.3 provides 4. Alternate Priority: The encoding specified in Section 2.3 provides
for a new priority and DEI in the Inner.Label First Part and a for a new priority and DEI in the Inner.Label First Part and a
place to preserve the original user priority and DEI in the Second place to preserve the original user priority and DEI in the Second
Part, so it can be restored on egress. Part, so it can be restored on egress.
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8. Allocation Considerations 8. Allocation Considerations
Allocations by the IEEE Registration Authority and IANA are listed Allocations by the IEEE Registration Authority and IANA are listed
below. below.
8.1 IEEE Allocation Considerations 8.1 IEEE Allocation Considerations
The IEEE Registration Authority has assigned EtherType 0x893B for use The IEEE Registration Authority has assigned Ethertype 0x893B for use
as the EX-TAG EtherType. as the FGL Ethertype.
8.2 IANA Considerations 8.2 IANA Considerations
IANA is requested to allocate capability bit TBD (0 recommended) in IANA is requested to allocate capability bit TBD in the TRILL-VER
the TRILL-VER sub-TLV capability bits [RFC6326bis] to indicate an sub-TLV capability bits [RFC6326bis] to indicate an RBridge is FGL-
RBridge is FGL-capable. capable.
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
9. Security Considerations 9. Security Considerations
See [RFC6325] for general RBridge Security Considerations. See [RFC6325] for general RBridge Security Considerations.
As with any communications system, end-to-end encryption and As with any communications system, end-to-end encryption and
authentication should be considered for sensitive data. authentication should be considered for sensitive data.
Confusion between a frame with VL X and FGL (X.Y) is a potential Confusion between a frame with VL X and FGL (X.Y) is a potential
problem: problem if a VL RBridge did not check for the occurrence of 0x8100
(see Sections 2.2 and 2.3) and discard such a frame. Possible
problems with such a VL RBridge would be as follows:
1. A TRILL Data frame with FGL (X.Y) could be egressed to an end 1. If it received a TRILL Data frame with FGL (X.Y) it could egress
station in VLAN-X by a VL RBridge that is Appointed Forwarder for it to an end station in VLAN-X. The payload of such an egressed
VLAN-X on one of its ports. This is solved by prohibiting FGL frame would appear to begin with Ethertype 0x893B which would
RBridges from ingressing to FGL (X.Y) if the campus is configured likely be discarded by an end station. Nevertheless, such an
so that VLAN-X is VL-specifiable (see Section 4.1). egress would almost certainly be a violation of security policy.
2. An end station could try to forge FGL (X.Y) frames by sending 2. If it received a multi-destination TRILL Data frame with FGL (X.Y)
frames with an EX-TAG Y at the front to a VL RBridge port where and it pruned the distribution tree, it would incorrectly prune it
the frame would be input as being in VLAN-X. This is solved by on the basis of VLAN-X. This could lead to the multi-destination
prohibiting egress from FGL (X.Y) while VLAN-X is VL-specifiable data frame not being delivered to all of its intended recipients.
(see Section 4.1).
These two potential problems would only occur in the case of the
misconfiguration of attaching such a VL RBridge to an FGL campus;
however, there is protection against this in that FGL RBridges will
not announce adjacency to VL RBridges (see Section 4). As a result,
no TRILL data frames can be exchanged between VL and FGL RBridges and
VL RBridges will be isolated for data puposes.
Acknowledgements Acknowledgements
The comments and contributions of the following are gratefully The comments and suggestions of the following are gratefully
acknowledged: acknowledged:
Anoop Ghanwani, Sujay Gupta, Weiguo Hao, Jon Hudson, Yizhou Li, Anoop Ghanwani, Sujay Gupta, Weiguo Hao, Jon Hudson, Yizhou Li,
Vishwas Manral, Erik Nordmark, Tissa Senevirathne, and Ilya Vishwas Manral, Erik Nordmark, and Ilya Varlashkin.
Varlashkin.
The document was prepared in raw nroff. All macros used were defined The document was prepared in raw nroff. All macros used were defined
within the source file. within the source file.
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
Normative References Normative References
[IS-IS] - ISO/IEC 10589:2002, Second Edition, "Intermediate System to [IS-IS] - ISO/IEC 10589:2002, Second Edition, "Intermediate System to
Intermediate System Intra-Domain Routeing Exchange Protocol for Intermediate System Intra-Domain Routeing Exchange Protocol for
skipping to change at page 18, line 27 skipping to change at page 20, line 27
[RFC2119] - Bradner, S., "Key words for use in RFCs to Indicate [RFC2119] - Bradner, S., "Key words for use in RFCs to Indicate
Requirement Levels", BCP 14, RFC 2119, March 1997 Requirement Levels", BCP 14, RFC 2119, March 1997
[RFC6325] - Perlman, R., Eastlake 3rd, D., Dutt, D., Gai, S., and A. [RFC6325] - Perlman, R., Eastlake 3rd, D., Dutt, D., Gai, S., and A.
Ghanwani, "Routing Bridges (RBridges): Base Protocol Ghanwani, "Routing Bridges (RBridges): Base Protocol
Specification", RFC 6325, July 2011. Specification", RFC 6325, July 2011.
[RFC6326bis] - Eastlake, D., Banerjee, A., Dutt, D., Perlman, R., and [RFC6326bis] - Eastlake, D., Banerjee, A., Dutt, D., Perlman, R., and
A. Ghanwani, "Transparent Interconnection of Lots of Links A. Ghanwani, "Transparent Interconnection of Lots of Links
(TRILL) Use of IS-IS", draft-eastlake-isis-rfc6326bis-01.txt, (TRILL) Use of IS-IS", draft-ietf-isis-rfc6326bis, work in
work in progress. progress.
Informative References Informative References
[RFC5556] - Touch, J. and R. Perlman, "Transparent Interconnection of [RFC5556] - Touch, J. and R. Perlman, "Transparent Interconnection of
Lots of Links (TRILL): Problem and Applicability Statement", Lots of Links (TRILL): Problem and Applicability Statement",
RFC 5556, May 2009. RFC 5556, May 2009.
[RFC6165] - Banerjee, A. and D. Ward, "Extensions to IS-IS for [RFC6165] - Banerjee, A. and D. Ward, "Extensions to IS-IS for
Layer-2 Systems", RFC 6165, April 2011. Layer-2 Systems", RFC 6165, April 2011.
skipping to change at page 20, line 5 skipping to change at page 21, line 13
6439, November 2011. 6439, November 2011.
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Change History Change History
From -00 to -01: From -00 to -01:
Update author info and make editorial changes. Update author info and make editorial changes.
From -01 to -02
1. Change the value after the inner MAC addresses for FGL frames from
0x8100 to 0x893B
2. As a consequence of item 1 above, for safety prohibit use for
TRILL Data of links between FGL and VL RBridges, isolating any VL
RBridges. Make appropriate changes throughout document, including
Security Considerations section, based on this change.
3. Reference and contributor updates.
4. Various editorial changes.
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
Authors' Addresses Authors' Addresses
Donald Eastlake 3rd Donald Eastlake 3rd
Huawei Technologies Huawei Technologies
155 Beaver Street 155 Beaver Street
Milford, MA 01757 USA Milford, MA 01757 USA
Phone: +1-508-333-2270 Phone: +1-508-333-2270
Email: d3e3e3@gmail.com Email: d3e3e3@gmail.com
Mingui Zhang Mingui Zhang
Huawei Technologies Co.,Ltd Huawei Technologies Co., Ltd
Huawei Building, No.156 Beiqing Rd. Huawei Building, No.156 Beiqing Rd.
Z-park ,Shi-Chuang-Ke-Ji-Shi-Fan-Yuan,Hai-Dian District, Z-park, Shi-Chuang-Ke-Ji-Shi-Fan-Yuan, Hai-Dian District,
Beijing 100095 P.R. China Beijing 100095 P.R. China
Email: zhangmingui@huawei.com Email: zhangmingui@huawei.com
Puneet Agarwal Puneet Agarwal
Broadcom Corporation Broadcom Corporation
3151 Zanker Road 3151 Zanker Road
San Jose, CA 95134 USA San Jose, CA 95134 USA
Phone: +1-949-926-5000 Phone: +1-949-926-5000
skipping to change at page 20, line 42 skipping to change at page 22, line 42
Radia Perlman Radia Perlman
Intel Labs Intel Labs
2200 Mission College Blvd. 2200 Mission College Blvd.
Santa Clara, CA 95054 USA Santa Clara, CA 95054 USA
Phone: +1-408-765-8080 Phone: +1-408-765-8080
Email: Radia@alum.mit.edu Email: Radia@alum.mit.edu
Dinesh G. Dutt Dinesh G. Dutt
Cumulus Networks
1089 West Evelyn Avenue
Sunnyvale, CA 94086 USA
Email: ddutt.ietf@hobbesdutt.com Email: ddutt.ietf@hobbesdutt.com
INTERNET-DRAFT TRILL: Fine-Grained Labeling INTERNET-DRAFT TRILL: Fine-Grained Labeling
Copyright, Disclaimer, and Additional IPR Provisions Copyright, Disclaimer, and Additional IPR Provisions
Copyright (c) 2012 IETF Trust and the persons identified as the Copyright (c) 2012 IETF Trust and the persons identified as the
document authors. All rights reserved. document authors. All rights reserved.
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